Our Bit Synchronizers reconstruct the input data stream and recover the clock with the highest fidelity to allow the processing system to produce the most meaningful information.
As a key component in a telemetry ground station, the PCM Bit Synchronizer must reconstruct its input data stream and recover the clock with the highest fidelity to allow the processing system to produce the most meaningful information.
Our Bit Synchronizers are better than 1dB from theory all the way down to –3dB Eb/No, at input signal levels down to 100mV. Above all of the other performance items, this is a major discriminator between the GDP Bit Synchronizer and other Bit Synchronizers on the market today. This translates to significantly less lock dropouts on down stream frame synchronizers and decommutators, resulting in significantly more usable data during receiver fade and multi-path situations, typically occurring at the most critical part of the mission, when the aircraft is performing the test maneuver.
Real world data integrity is very sensitive to Bit Synchronizer jitter performance. Static bit error rate tests do not evaluate bit synchronizers under real world conditions. Real world signals are affected by jitter which adversely affects the data recovery ability of a bit synchronizer. This is further exasperated when multiple bit synchronizers are connected in series.
See our Technical Paper: ‘Series Connected Bit Synchronizers Need Sequentially Increased Loop Bandwidths‘ for more information. Proper evaluation of bit synchronizer performance in the presence of jitter can be measured using the GDP Model 650 Bit Error Rate Test Set with the jitter test option.
- Superior Bit Error and Jitter Performance
- Built-in BERT / Frame Sync
- QPSK, OQPSK, SOQPSK Merging
- Best Source DQE/DQM Output
- 10 bps to 40+ Mbps
- Single or Multi-channel Rackmount Units
- Single or Dual-channel PCI Cards