Bit Synchronizers

Model 2365A Multi-Channel Touch-Screen PCM Bit Synchronizer
Model 2365A Multi-Channel Touch-Screen PCM Bit Synchronizer

The GDP Model 2365A Multi-Channel PCM Bit Synchronizer houses up to 8 high-performance bit synchronizer channels in a 4U chassis. The optimized digital design of this unit affords the highest performance characteristics currently available.

Control and monitoring of all parameters and features is accomplished by way of the local control interface using a PC, mouse (optional touch-screen) and keyboard. Remote control of the unit is through an Ethernet interface. (Other interfaces are available.)

The bit synchronizers are capable of maintaining synch at –3 dB Eb/No with signal levels as low as 0.1 Vp-p. Search acquisition is attainable in less than 50 bits and synchronization is maintained for a period of at least 256 bit periods without a transition.

Two Analog inputs are provided per channel. Optional digital inputs for RS-422 and TTL levels may be included. Each channel presents a variety of standard outputs to support complex system requirements. (Special outputs are available.)

A standard IRIG 106 randomizer/derandomizer (forward and reverse) is included as is a CCITTV.35 and V.36 descrambler. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7and R1/3 k7 (please inquire for other FEC options). Reed Solomon Decoding is an available option.

The Pattern Detector adds an additional level of synchronization assurance by invoking the Frame Pattern Detector. Automatic Polarity Correction (APC) may be invoked when using the Pattern Detector.

Data-stream quality is measured and reported to the user in the form of: Eb/No, Frame Synch Pattern BER / Viterbi Decoder CER. A data stream generator / simulator is available to facilitate system testing, and providing a BERT function.

An Auto Scan feature is available that allows the bit synchronizers to scan the input for up to 8 pre-selected bit rates, input codes and frame patterns. When an acceptable signal is present, the Bit Synchronizer automatically locks to it and recovers the data and clock. Should this signal drop-out, the bit synchronizer reinitiates the scan sequence.

  1. Up to 8-Channels in 4U
  2. Bit Rate Range:
  3.      • 5 bps to 20 Mbps
         • 5 bps to 40 Mbps (Option)
  4. Performance within 1 dB of theory
  5. Loop Bandwidth Settings from 0.01% to 1.6%
  6.      • Extended LBW Range (Option)
  7. NRZ-L/M/S; BiØ-L/M/S; DMM/S; MDM-M/S
  8. Randomizer/Derandomizer
  9. Descrambler
  10.      • CCITT V.35 / V.36
  11. Viterbi Decoder
  12. Frame Pattern Detector
  13. Input Signal Status
  14.      • Bit Sync and Signal Loss
         • Pattern Detector Status
         • Viterbi Decoder Status
         • Bit Rate Deviation
         • Signal Level
  15. Signal/Data Quality Status
  16.      • Eb/No Measurement
         • Frame Sync Pattern Error Count (BER)
         • Frame Loss Count
         • Viterbi Error Count (CER)
         • BERT/ PRN BER Measurement
  17. Date Generator/Simulator
  18.      • Serial
         • QPSK (Option)
  19. Advanced Lock Detection
  20. Auto Bit-Rate Scan (Option)
  22. Resequencer (Option)
  23. Remote Control
  24.      • Ethernet
         • RS-232 or IEEE-488 (Option)
  25. 7 -inch High Chassis
Inputs, each Bit Sync:
Analog Inputs
2 Inputs per Bit Sync- 50 Ohms (optional 75Ω) or High Z.
Digital Inputs
Differential RS-422 and TTL (Optional) [Ask about other configurations]

Bit Rate Range
5 bps to 20 Mbps (40 Mbps Optional)
Tuning Resolution
X.XXXEN (1≤N≤7)
Input Levels
0.1 Vp-p Min., ± 12 V Max.. (others available)
DC Offsets
100% of the input peak-to-peak signal level.
AC Offset
No degradation up to 100% of input signal amplitude at 0.1% of the bit rate.
Loop Bandwidths
0.01% to 1.6% (Extended LBW Range Optional)
Acquisition Range
2x LBW
Sync Acquisition
Threshold SNR 0 dB
Sync Maintenance
SNR –3 dB
Sync Acquisition
= 50 bits
Sync Retention
256 bits without transitions
Bit Error Rate
1 dB to 40 Mbps

Input/Output PCM Codes
Randomizer / Derandomizer
IRIG 106 forward and reverse
CCITT V.35 / V.36
Viterbi Decoder
R 1/2, K 7 with G1/G2 Swap and G2 Invert, (others available)
QPSK / OQPSK / SOQPSK (Optional)
Frame Pattern Detector
Up to 64 bits with programmable strategy and APC
Auto Scan (Optional)
Up to 8 preset: Bit Rate, Code, Frame pattern per Bit Synchronizer.
Output Data Polarity
Normal / Inverted.
Output Clock Phase
0º, 90º, 180º, 270º to 20 Mbps; 0º, 180º in the range 20 Mbps to 40 Mbps.
BERT Function (option)
Bit-Error-Rate PRN Generator/Error Detector

Outputs, each Bit Sync Channel:
TTL (Each Channel)
Coded PCM and Clock (Programmable 0º, 90º, 180º, 270º)
RS422 (Each Channel)
Coded PCM and Clock (Programmable 0º, 90º, 180º, 270º)
Bipolar Tape Output (Each Channel)

1Vp-p - Coded PCM (Other Output Configurations are available.)
Lock Status for each channel
Signal Quality Status:
Eb/No, Bit Rate Deviation, BERT / PRN BER or Viterbi CER Measurements