Model 270 Multi-Channel Bit Synchronizer with Digital IO
  • Eight or sixteen independent channels that each have both TTL and RS-422 inputs and outputs
  • Compact, state-of-the-art high-performance device
  • Unbeaten performance in jitter and noise in worldwide side-by-side testing
  • Superior Jitter Performance Unmatched in the Industry
  • Better than 1db from theory all the way down to -3dB Eb/No
  • Internal Frame Sync Pattern Detectors and Viterbi Decoders for each channel

The GDP Model 270 Multi-Channel (8 or 16 Channels) Bit Synchronizer unit with Digital I/O is a compact state-of-the-art high-performance device that is designed to extract usable digital data and provide an output clock from serial digital input streams.  The optimized digital design of this unit affords the highest performance characteristics currently available. Eight additional channels can be added (16 channels total) to the box as an option.

The Model 270 includes eight or sixteen independent channels that each have both TTL and RS-422 inputs and outputs. The unit includes programmable loop bandwidths from 0.05% to 1.6%. When searching for the signal, acquisition is attainable in as little as 40 bits. At the widest LBW the unit will track the signal to 15% of the input rate. Synchronization is maintained in the absence of transitions for a period of at least 128 bits.

Encoded data streams are processed to expose the raw information. IRIG-106 Randomized data is decoded to its native form. Both forward and reverse sequences are accommodated.

To further assure synchronization to the intended data stream, the optional Frame Pattern Detector may be invoked. Up to a 64-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. The unit also includes an APC (Automatic Polarity Correction) mode. In this mode, the output polarity of the data will be corrected.

When the input bit rate is expected to be changing, use the optional Auto Bit Rate Scan. Up to 8 bit rates, input codes and Synchronization patterns can be programmed. The bit synchronizer automatically finds the appropriate setting from the list and locks to the input signal. To add accuracy to the lock decision, the Frame Pattern Detector be included in the test. Status for each of the streams along with selected bit rate and deviation are displayed on the front panel.

Model 270 Multi-Channel Bit Synchronizer with Digital IO
  • Eight or sixteen independent channels that each have both TTL and RS-422 inputs and outputs
  • Compact, state-of-the-art high-performance device
  • Unbeaten performance in jitter and noise in worldwide side-by-side testing
  • Superior Jitter Performance Unmatched in the Industry
  • Better than 1db from theory all the way down to -3dB Eb/No
  • Internal Frame Sync Pattern Detectors and Viterbi Decoders for each channel

The GDP Model 270 Multi-Channel (8 or 16 Channels) Bit Synchronizer unit with Digital I/O is a compact state-of-the-art high-performance device that is designed to extract usable digital data and provide an output clock from serial digital input streams.  The optimized digital design of this unit affords the highest performance characteristics currently available. Eight additional channels can be added (16 channels total) to the box as an option.

The Model 270 includes eight or sixteen independent channels that each have both TTL and RS-422 inputs and outputs. The unit includes programmable loop bandwidths from 0.05% to 1.6%. When searching for the signal, acquisition is attainable in as little as 40 bits. At the widest LBW the unit will track the signal to 15% of the input rate. Synchronization is maintained in the absence of transitions for a period of at least 128 bits.

Encoded data streams are processed to expose the raw information. IRIG-106 Randomized data is decoded to its native form. Both forward and reverse sequences are accommodated.

To further assure synchronization to the intended data stream, the optional Frame Pattern Detector may be invoked. Up to a 64-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. The unit also includes an APC (Automatic Polarity Correction) mode. In this mode, the output polarity of the data will be corrected.

When the input bit rate is expected to be changing, use the optional Auto Bit Rate Scan. Up to 8 bit rates, input codes and Synchronization patterns can be programmed. The bit synchronizer automatically finds the appropriate setting from the list and locks to the input signal. To add accuracy to the lock decision, the Frame Pattern Detector be included in the test. Status for each of the streams along with selected bit rate and deviation are displayed on the front panel.

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