Model 650 Single Channel Data Transmission Test Set
  • Data link test, analysis, and validation
  • Comprehensive Bit Synchronizer Testing with internal noise source
  • Independent Transmitter and Receiver
  • IRIG Bit-coding, Convolutional Encoding and LDPC formats
PRODUCT DESCRIPTION

The GDP Model 650 Data Transmission Test Set fills the need for high performance data-link verification and qualification at an affordable price. The user is provided with totally independent transmit and receive functions to allow rapid fault isolation and data link characterization. Simulated signal perturbations are created in the test lab by adding noise, baseline offset and varying signal levels. Features such as an internal 6-digit frequency synthesizer and IRIG Code generator and converter make the Model 650 especially suited to the test and evaluation of PCM Telemetry data link systems and components.

The Model 650 provides measurement capability for: Accumulated Bit Errors, Measured Bit Error Rate, Elapsed Test Time, Accumulated Errored Seconds, Errors per Second, Measured error Symmetry, Accumulated Bit Count Integrity loss (Bit Slips), Measured Transmit and Receive clock rate.

Operating ease and test flexibility is the result of using microprocessor control to augment high speed hardware functions. A high contrast vacuum fluorescent display provides setup and test result information in easy-to-use formats.

Functional Description

A modular architecture gives the Model 650 superior flexibility. A fully programmable frequency synthesizer allows transmit clock generation from 1 bps to 50 Mbps with 6-digit resolution. A flexible interface structure, which provides IRIG code converters for both input and output data, allows the Model 650 to fully support test and evaluation of telemetry receive, and processing systems.

The BER (Bit Error Rate) Module, is the major functional element in the Model 650. A microprocessor resident on the BER module controls the BERT transmit and receive circuits through user commands issued from the local front panel or remote control port. Communication between the microprocessor module and the BER module is accomplished using semaphores passed into a dual-port RAM architecture.

All high-speed functions are provided by hardware Functions such as data generation, PRN correlation, error detection and accumulation are performed by hardware. Low speed functions, such as test data accumulation and formatting for the front panel and remote monitoring ports, are provided by the embedded microprocessors.

SPECIFICATIONS
GENERAL
OPERATION:
Independent Transmitter and Receiver
1 bps to 36 Mbps NRZ codes (17.5 Mbps for 2X codes) Standard
1 bps to 50 Mbps NRZ codes (30 Mbps for 2X codes) Optional
TTL-50 Mbps, Bipolar-40 Mbps, RS-422-40 Mbps
Frequency Display:
Receive and Transmit Bit Rate, Measured
INPUT TERMINATION:
High Z / Low-Z on TTL & Bipolar
DATA PATTERN SELECTABLE:
Forward & Reverse PRN codes:
25-1, 27-1, 29-1, 211-1, 215-1, 217-1, 219-1, 220-1, 223-1, 225-1, 231-1,
User selectable Taps
Recycle data patterns, programmable:
8, 16, 24, 32, 64, 128, 256 bits
or Dotting pattern
IRIG Bit-Codes:
NRZ-L/M/S; BiØ-L/M/S; DM-M/S
DATA RANDOMIZER / DERANDOMIZER:
V.35, V.36 or FWD/REV RNRZ-L 2N-1(N=15 [IRIG-STD 106], 9, 11, 17, 23)
CONVOLUTIONAL ENCODER (VITERBI DECODER):
Option:
Rate ½ ; K 7
Selectable convolution order and polarity
TRANSMITTER
DATA/CLOCK OUTPUTS:
Transmit I-and Q (Option)-Data
Transmit Clock
CLOCK INPUT:
External Transmit Clock
Selectable
TRANSMIT TIMING:
Internal Frequency Synthesizer
Six (6) digit-plus-exponent
DATA PERTURBATIONS:
Force output
ALL 1s or ALL 0s
Insert a single error
Insert a single slip
Insert bit-error-rates
From 1.0E-06 to 0.5
Insert Gap
Selectable data slip
Up to 9999 bit times
Selectable data gap
Up to 9999 bit times
Bit Rate Jitter
Option
AC Base-line Variation
With Analog Option
Signal Amplitude Modulation
With Analog Option
RECEIVER
RECEIVE DATA AND CLOCK, SYNCHRONIZATION:
Auto Polarity Correction
Auto-correlation BER up to 3 x 10-1
ReSynch Threshold, Selectable
Error Allowance Threshold
TESTS:
Test length from 102 thru 1012 bits
Total Count since test start:
Bits
Bits-in-Error
Seconds
Erred-Seconds
Slips
Calculations:
Bit-Error Rate
Symmetry
Average Bit-Error Rate
Sync Acquisition (Option)
Data Link Delay (Option)
BER vs Eb/No Performance
Jitter Performance
ANALOG INTERFACE (OPTION)
TRANSMIT DATA WITH LEVEL AND OFFSET ADJUST:
Signal level:
100 mVp-p to 4 Vp-p (50 ΩLoad)
DC offset:
Up to +5V or – 5V (Peak signal + Offset + Noise)
AC Offset
Bit Rate Jitter
NOISE:
Options:
Internal programmable Eb/No generator
External Noise Input
LOCAL FRONT PANEL CONTROL
Power ON/OFF
Display and Keypad
Soft Control Keys
LED Status and Test Points
MISCELLANEOUS
AC Input:
90 to 264 VAC Auto-set
Single Phase, 47-63 Hz
Size:
3.5 (H) x 20 (D) x 17 (W), inches
Weight:
20 lbs.
Mounting:
19 inch EIA rack mount
ENVIRONMENT, OPERATING:
Temperature:
0 to 40° C
Relative Humidity:
5 to 95%, no condensation
Altitude:
0 to 10,000 ft
Forced-air Cooling
REMOTE CONTROL
RS-232 Serial Interface
Standard
IEEE488 Interface
Optional
Ethernet
10/100 Base T
Optional
Model 650 Single Channel Data Transmission Test Set
  • Data link test, analysis, and validation
  • Comprehensive Bit Synchronizer Testing with internal noise source
  • Independent Transmitter and Receiver
  • IRIG Bit-coding, Convolutional Encoding and LDPC formats
PRODUCT DESCRIPTION

The GDP Model 650 Data Transmission Test Set fills the need for high performance data-link verification and qualification at an affordable price. The user is provided with totally independent transmit and receive functions to allow rapid fault isolation and data link characterization. Simulated signal perturbations are created in the test lab by adding noise, baseline offset and varying signal levels. Features such as an internal 6-digit frequency synthesizer and IRIG Code generator and converter make the Model 650 especially suited to the test and evaluation of PCM Telemetry data link systems and components.

The Model 650 provides measurement capability for: Accumulated Bit Errors, Measured Bit Error Rate, Elapsed Test Time, Accumulated Errored Seconds, Errors per Second, Measured error Symmetry, Accumulated Bit Count Integrity loss (Bit Slips), Measured Transmit and Receive clock rate.

Operating ease and test flexibility is the result of using microprocessor control to augment high speed hardware functions. A high contrast vacuum fluorescent display provides setup and test result information in easy-to-use formats.

Functional Description

A modular architecture gives the Model 650 superior flexibility. A fully programmable frequency synthesizer allows transmit clock generation from 1 bps to 50 Mbps with 6-digit resolution. A flexible interface structure, which provides IRIG code converters for both input and output data, allows the Model 650 to fully support test and evaluation of telemetry receive, and processing systems.

The BER (Bit Error Rate) Module, is the major functional element in the Model 650. A microprocessor resident on the BER module controls the BERT transmit and receive circuits through user commands issued from the local front panel or remote control port. Communication between the microprocessor module and the BER module is accomplished using semaphores passed into a dual-port RAM architecture.

All high-speed functions are provided by hardware Functions such as data generation, PRN correlation, error detection and accumulation are performed by hardware. Low speed functions, such as test data accumulation and formatting for the front panel and remote monitoring ports, are provided by the embedded microprocessors.

SPECIFICATIONS
GENERAL
OPERATION:
Independent Transmitter and Receiver
1 bps to 36 Mbps NRZ codes (17.5 Mbps for 2X codes) Standard
1 bps to 50 Mbps NRZ codes (30 Mbps for 2X codes) Optional
TTL-50 Mbps, Bipolar-40 Mbps, RS-422-40 Mbps
Frequency Display:
Receive and Transmit Bit Rate, Measured
INPUT TERMINATION:
High Z / Low-Z on TTL & Bipolar
DATA PATTERN SELECTABLE:
Forward & Reverse PRN codes:
25-1, 27-1, 29-1, 211-1, 215-1, 217-1, 219-1, 220-1, 223-1, 225-1, 231-1,
User selectable Taps
Recycle data patterns, programmable:
8, 16, 24, 32, 64, 128, 256 bits
or Dotting pattern
IRIG Bit-Codes:
NRZ-L/M/S; BiØ-L/M/S; DM-M/S
DATA RANDOMIZER / DERANDOMIZER:
V.35, V.36 or FWD/REV RNRZ-L 2N-1(N=15 [IRIG-STD 106], 9, 11, 17, 23)
CONVOLUTIONAL ENCODER (VITERBI DECODER):
Option:
Rate ½ ; K 7
Selectable convolution order and polarity
TRANSMITTER
DATA/CLOCK OUTPUTS:
Transmit I-and Q (Option)-Data
Transmit Clock
CLOCK INPUT:
External Transmit Clock
Selectable
TRANSMIT TIMING:
Internal Frequency Synthesizer
Six (6) digit-plus-exponent
DATA PERTURBATIONS:
Force output
ALL 1s or ALL 0s
Insert a single error
Insert a single slip
Insert bit-error-rates
From 1.0E-06 to 0.5
Insert Gap
Selectable data slip
Up to 9999 bit times
Selectable data gap
Up to 9999 bit times
Bit Rate Jitter
Option
AC Base-line Variation
With Analog Option
Signal Amplitude Modulation
With Analog Option
RECEIVER
RECEIVE DATA AND CLOCK, SYNCHRONIZATION:
Auto Polarity Correction
Auto-correlation BER up to 3 x 10-1
ReSynch Threshold, Selectable
Error Allowance Threshold
TESTS:
Test length from 102 thru 1012 bits
Total Count since test start:
Bits
Bits-in-Error
Seconds
Erred-Seconds
Slips
Calculations:
Bit-Error Rate
Symmetry
Average Bit-Error Rate
Sync Acquisition (Option)
Data Link Delay (Option)
BER vs Eb/No Performance
Jitter Performance
ANALOG INTERFACE (OPTION)
TRANSMIT DATA WITH LEVEL AND OFFSET ADJUST:
Signal level:
100 mVp-p to 4 Vp-p (50 ΩLoad)
DC offset:
Up to +5V or – 5V (Peak signal + Offset + Noise)
AC Offset
Bit Rate Jitter
NOISE:
Options:
Internal programmable Eb/No generator
External Noise Input
LOCAL FRONT PANEL CONTROL
Power ON/OFF
Display and Keypad
Soft Control Keys
LED Status and Test Points
MISCELLANEOUS
AC Input:
90 to 264 VAC Auto-set
Single Phase, 47-63 Hz
Size:
3.5 (H) x 20 (D) x 17 (W), inches
Weight:
20 lbs.
Mounting:
19 inch EIA rack mount
ENVIRONMENT, OPERATING:
Temperature:
0 to 40° C
Relative Humidity:
5 to 95%, no condensation
Altitude:
0 to 10,000 ft
Forced-air Cooling
REMOTE CONTROL
RS-232 Serial Interface
Standard
IEEE488 Interface
Optional
Ethernet
10/100 Base T
Optional
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