Real Time PCM Frame Sync/Decommutator
Model 1632AP Card Embedded Programmable Low Latency Frame Sync/Decom/Data Output Formatter
To four program selectable decom inputs supported, TTL NRZ-L Data and 0º Clock. When configured with optional Model 674DM bit sync a fifth program selectable internal bit sync input path is provided.
50 Ohm input impedance, TTL compatible.
From 0 to 50+ Mbps, burst, jam, and streaming mode compatible.
Programmable, automatic polarity correction.
Programmable, 1 to 32 bit word length for each input.
Programmable, MSB/LSB orientation for each input word.
Selectable leading, trailing, or no parity checking for each word.
Provides for programmable sync pattern and mask, complement pattern recognition, and variable length frame decommutation. The pattern may be up to 64 bits in length.
Six independent synchronizers are capable of decommutating sub-frames within subframes. Subframes synchronize to fixed recycle patterns, complement frame sync patterns, and various ID patterns. Both recycle and ID patterns may be assembled from multiple word locations. Recycle patterns may be up to 32 bits long.
Two types of ID synchronization are supported: JAM patterns of arbitrary values, and incrementing or decrementing frame counters with limit checking. ID sync words may be up to 16 bits in length.
Programmable Search-Check-Lock sync strategy, bit error tolerance, and bit slip window provide reliable frame synchronization.
Subframe synchronizer may be programmed to decommutate embedded formats having unique frame sync patterns and format structures.
16 testable flags store the results of select input stream bit and word comparisons to control real-time format switching Frame Sync / Decom format switching is loss-less and immediate. Multiple card resident micro-coded decom processing programs are stored in local decom memory in support of such conditional format switching events.
Standalone Data Output
Data is available to the host computers PCI bus as memory-mapped frame buffers, Current Value Table (CVT), or as a data stream selectably transferred by PCI bus DMA. Data is 32 bits with programmable MSB/LSB output word justification, sign extension, or zero insertion for LSB output. Acroamatics Telemetry System Software (ATSS) suite provides a host of Windows compatible (XP and Windows 7 compatible) which support user decom set-up, mission set-up management, and a host of real-time data display, alarming, recording, discrete/analog, and networked data I/O processes and local operator status display, and remote system management and data operations support.
I-Buss Data Output
When used in a system configured with new 1635AP PDSP PCeI advanced telemetry processing module(s), the Model 1612AP uses a 64 bit parallel “I-bus” low latency inter-card connection that processes messages containing thirty two bits of data, twelve bits of fine time (microseconds), two bits of status, and 17 bits of data identification. I-bus data can be formatted in either MSB or LSB justified form. LS-justified data can also be sign extended. I-bus decom data is transmitted to the 1605P or new 1615AP PDSP card resident distribution & algorithmic data processor. The 1635AP is capable of from up merging data from any of up to eight 1632AP cards in a system, to form the desired EU processing data and formatted data output products in support of real-time analog (DAC) output, raw or processed data recording, real-time display, and networked data communications processes. Decom and bit sync data quality status words are generated for downstream data validation, as well.
2 Serial PCM Outputs
Two user program controlled RS-422 compatible serial output channels are available
Model 1632AP Card Embedded User Programmable 1 bps – 64 Mbps PCM Simulator/Encoder
PCM Programmable PCM Format Simulator/Encoder Functions
Stores two complete, selectable PCM formats. Performs asynchronous frame insertion and format switching
Generates up to three subframes within mainframe. Generates subframe within subframe
Up to 65,536 words for the mainframe and 16,384 per subframe
1M unique user defined static ans 64k dynamic word registers. Two complete user-defined onboard stream simulation data memories. Two 16-bit module up/down counters. Two 16-bit external inputs. One 16-bit pseudo-random number generator. One 16-bit program counter.
Programmable for each data source: static data words 1 to 32 bits; all others 1 to 16 bits
Program selectable: MSB/LSB for each data word
Program selectable: leading, trailing, or no parity for each data word
Dynamic Data Memories
2 unique, user-defined 6kB RAM’s. Presettable to ramp, sine, triangle and squarewave functions or user-defined input. Selectable data type: 1’s complement, 2’s complement, signed magnitude, offset binary. Programmable time base.
Program selectable: 1Hz to 64 Mbps, tunable to 0.1% of programmed rate
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RNRZ 11/15/17/23
TTL compatible NRZ-L data and 0º clock
Model 674DM(Option – companion mezzanine module to Model 1632AP
Two each analog baseband user selectable PCM inputs – #1 single-ended, #2 single-ended or RS-422
greater than 60dB at 20MHz
Program selectable: Hi-Z/Lo-Z, Single Ended 4kΩ/75Ω , Differential: 10kΩ /150Ω
Single Ended: 0.2-20V P-P, Differential: 0.2-10V P-P
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, MDM-M/S, RZ
Program selectable: RNRZ 9/11/15/17/23, forward/reverse
IRIG Time Code Reader/Generator
Model 470M(Option – companion mezzanine module to Model 1612P, one per system)
IRIG Time Code Reader/Generator/Translator
0.5 to 20 Vpp, Single-ended
12K Ohms minimum
Translates IRIG G, A, B, & NASA-36
125 Hz to 400,000 Hz
2:1 through 5:1
Program selectable: Invert or Normal Polarity
Time Base 40MHz crystal oscillator
Time is generated from the onboard crystal oscillator and is pre-settable from the Host
Time is read from an external source
Translate Carrier Mode
The internal timing is based on the input carrier. This mode enables the system to translate time as the input carrier rate varies during playback of an analog recording
Translate Failsafe Mode
The internal timing is phase-locked to the input carrier. In the event of time dropout, the translator continues generating time without interrupt
Automatic frame bypass compares previous time frame with current one, and Time Accumulator updates when they agree
Specifications subject to change without notice.