Simulation & Link Validation

Testing a data link can be a complex activity. The GDP BERT products all include full and independent transmit and receive paths. Generated test data streams are monitored at the return link where errors are detected and reported. Test data may be manipulated to produce intentional errors to simulate unique conditions so as to stress the components of the link. Generated data can be standard maximal-length pseudo-random as well as fixed and user-defined patterns. Some optional features are also available that support stressing the unit(s) under test (i.e. Signal Level, DC / AC Signal Offset, Rate Jitter, Noise injection …).

Virtual Interface remote control software is available for control and plotting of test results (i.e. Noise performance, Jitter performance).

Model 650 Single Channel Data Transmission Test Set

Data Transmission Test Set – Data Transmission Test Set (Bit Error Rate Tester). 35 Mbps operation. Internal frequency synthesizer, IRIG Code Converter, RS232 Remote Control. 3/5″ chassis.

Model 652 Dual Channel Data Transmission Test Set (BERT)

Dual Channel Data Transmission Test Set – ECL & RS422 / TTL & RS422; Data Transmission Test Set (Bit Error Rate Tester). Internal frequency synthesizer, IRIG Code Converter, RS232 Remote Control. 3/5″ chassis.

Model 1650P Frame Sync Verification Unit

Acroamatics’ Model PCI 1650 FSVU (Frame Synchronization Verification Unit) contains eight PCM Decommutators that are designed for PCM stream quality verification.

Model 236 Programmable PCM Simulator

The GDP Space Systems Model 236 PCM/PAM Simulator addresses the need to perform cost effective PCM or PAM clock and data simulations.

Model 2618P PCM Frame Validation System

Acroamatics’ Model 2618P-16 PCM Frame Validation System will monitor as many as eight independent streams, providing a quick visual indication of the signal quality of PCM data and verification that the received data corresponds to the expected frame characteristics.