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Model 674DM 40 Mbps Advanced Dual PCM Bit Sync Mezzanine

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Model 674DM 40 Mbps Advanced Dual PCM Bit Sync Mezzanine
  • Two Independent Bit Syncs
  • Multiple Program Controlled Inputs and Outputs Tunable Bit Rate Range
  • Best in Class Noise Performance within 0.50 db of theoretical
  • Fast sync acquisition within 50 bit transitions, typical
  • Best in Class Sync Retention to 1024 bits without transition
  • Processes all IRIG Codes
  • Remote Software Operations

The 674DM Advanced Digital PCM Bit Sync is a state-of-the-art compact “mezzanine” design that provides a cost-effective and modular high-quality bit sync add-on to Acroamatics entire line of single slot PCI single card TM processing card products.

The 674DM is compatible with existing legacy and our latest telemetry card components. Based on our 3rd generation bit sync design, it shares the latest techniques in FIR filtering, digital phase-locked loop, NCO clock reconstruction, and digital amplitude and offset control with its larger PCI cousin, the Model 1611P. Incorporating a leading-edge FPGA, this modern design delivers a significantly reduced parts count, improved reliability, and expanded capabilities – including options normally found only in box level and multi-card bit sync/encoder designs. The 674DM supports options such as Frame Sync Pattern Verification, BERT, PRN and programmable PCM simulator, and Convolutional encode/decode.The Model 674DM PCM Bit Sync is fully compatible with legacy Acroamatics TDP system and remote Bit Sync utility software set-ups, easily meeting and exceeding all IRIG performance and functional requirements.

SIGNAL INPUTS (Per Bit Sync)
Source
Two (2) Inputs, Operator Program selectable, per Bit Sync Channel (Direct to companion decom & external)
Isolation
Greater than 60dB at 20MHz
Impedance
Program selectable: Hi-Z/Lo-Z, Single Ended: 4kΩ /75Ω (std) or differential: 150 Ohm or Hi-Z (opt)
Signal Level
0.2 to 20V p-p, Single-ended. Differential: 0.2 to 10V p-p, Differential (optional)
DC Offset
20V max Single-Ended, Hi-Z or 15V Max @ 75Ω
Baseline Variation
Tracks sinusoidal offsets to 100% p-p signal amplitude at 0.1% bit rate
PCM Codes
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
Derandomizer
Program selectable: RNRZ 9/11/15/17/23, forward/reverse
SYNCHRONIZATION
Bit Rate Range
8bps to 40MHz, all PCM Codes
Tuning Resolution
0.1% of bit rate
Capture Range
3 times the programmed loopwidth, typical
Tracking Range
±12% typical, with programmable limiter
Loop Bandwidth
0.1% to 3.2%, program selectable in 0.1% increments
Sync Threshold
0db for NRZ-L and Biø-L codes
Sync Maintenance
(LW=0.1%) –2dB NRZ-L and Biø-L codes
Sync Acquisition
(LW=1.6%, SNR > 12dB) Typically less than 50 bit periods
Sync Retention
(LW=0.1%, SNR > 3dB) Retains sync through > 1024 consecutive dropouts
Bit Error Rate
(LW=0.1%) to within .50 dB of ideal bit error rate performance curves
DATA/CLOCK OUTPUTS, NRZ-L Per Bit Sync
NRZ-L Data
One each, NRZ-L data/clock pair, RS422/TTL (jumper selectable) – operator program output selectable to INTERNAL (direct to host decom card via internet bus) or EXTERNAL (output pair directed to card external output BNC or Triax cables)
Data Clock
0°, 90°, 180°, 270°, operator program selectable
Data Polarity
Program selectable: normal/inverted
DATA/CLOCK OUTPUTS, CODE (Dual PCM Encoders) Per Bit Sync
Data Source
Program selectable: Recovered Data (Bit Sync NRZ-L Data/Clock – DEFAULT) or External Data/Clock (PROGRAM SELECTABLE).
Outputs
Three each: One each TTL data/clock (0° & 180° selectable) Code (selectable) PCM and Clock, One each TTL data RNRZL, One each TAPE (code selectable) TTL or ±2 Volts balanced output, 50mA drive current.
Randomizer
Program selectable: RNRZ 9/11/15/17/23, forward/reverse
PCM Codes
Program selectable: NRZ-L/M/S, Biø-L//M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
EXTERNAL DATA/CLOCK PCM ENCODER INPUT Per Bit Sync
Signal Type
Jumper selectable: RS-422 or TTL
Impedence
120Ω , RS-422, 75Ω TTL
Data Code
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
Data Clock
Program selectable: Normal/Inverted, 1x or 2x
CONVOLUTION ENCODER/DECODER (Optional)
Viterbi Decoder
Rate 1/2, k=7: includes differential decoding, V.35 descrambling, and G2 invert (others available)
Symbol Formats
Serial, parallel, and staggered parallel (others available)
Convolution Encoder
Rate 1/2, k=7: includes differential encoder, V.35 scrambler, and G2 inverter (others available)
Symbol Formats
Serial, parallel, and staggered parallel (others available)
FORMAT GENERATORS/SYNCHRONIZER (Optional)
Format Generator
Programmable frame length, sync pattern and mask
Synchronizer Source
Recovered data, external data or test generator
Synchronizer Strategy
Pattern match in “search”, programmable error limits for “check” and “lock” states
Other Features
Bit slip enable, auto polarity enable, data source/ambiguity resolution
BIT ERROR RATE TESTER (Optional)
Transmitter Pattern
PRN sequence: PN7, PN9, PN11, PN15 (forward/reverse)
Pattern Clock Source
Program selectable: Bit Rate Clock or External Clock
Blanking
Program selectable: 64, 128, 256 bits
BER Sample Period
Program selectable: 1E3 to 1E9 bit periods, or continuous accumulate
Variable Output
50mV to 5V P-P
Other Features
Automatic pattern sychronization, forced error ON/OFF
PHYSICAL
Hosts Supported
Plugs onto Models 1611P, 1626P, 1612P, & 1622P (PCI), 1632AP (PCIe), or RS232 Standalone
Cooling Requirements
30 Linear FPM
Power Requirements
+5VDC at 1.4A and +12VDC at  0.9A
Dimensions
6.5″ (16.51cm) H x 4.0″ (310.16cm) W x .625″ (1.5875cm) D
Temperature
Operating: 0° to +40° C, Non-operating -40° to 86° C
Relative Humidity
Up to 90% non-condensing
Shock
Operating 6G, Non-operating 25G
Vibration
Operating 0.3G, 5 to 2000 Hz, Non-operating 0.8G, 5 to 500 Hz

Specifications subject to change without notice.

Model 674DM 40 Mbps Advanced Dual PCM Bit Sync Mezzanine
  • Two Independent Bit Syncs
  • Multiple Program Controlled Inputs and Outputs Tunable Bit Rate Range
  • Best in Class Noise Performance within 0.50 db of theoretical
  • Fast sync acquisition within 50 bit transitions, typical
  • Best in Class Sync Retention to 1024 bits without transition
  • Processes all IRIG Codes
  • Remote Software Operations

The 674DM Advanced Digital PCM Bit Sync is a state-of-the-art compact “mezzanine” design that provides a cost-effective and modular high-quality bit sync add-on to Acroamatics entire line of single slot PCI single card TM processing card products.

The 674DM is compatible with existing legacy and our latest telemetry card components. Based on our 3rd generation bit sync design, it shares the latest techniques in FIR filtering, digital phase-locked loop, NCO clock reconstruction, and digital amplitude and offset control with its larger PCI cousin, the Model 1611P. Incorporating a leading-edge FPGA, this modern design delivers a significantly reduced parts count, improved reliability, and expanded capabilities – including options normally found only in box level and multi-card bit sync/encoder designs. The 674DM supports options such as Frame Sync Pattern Verification, BERT, PRN and programmable PCM simulator, and Convolutional encode/decode.The Model 674DM PCM Bit Sync is fully compatible with legacy Acroamatics TDP system and remote Bit Sync utility software set-ups, easily meeting and exceeding all IRIG performance and functional requirements.

SIGNAL INPUTS (Per Bit Sync)
Source
Two (2) Inputs, Operator Program selectable, per Bit Sync Channel (Direct to companion decom & external)
Isolation
Greater than 60dB at 20MHz
Impedance
Program selectable: Hi-Z/Lo-Z, Single Ended: 4kΩ /75Ω (std) or differential: 150 Ohm or Hi-Z (opt)
Signal Level
0.2 to 20V p-p, Single-ended. Differential: 0.2 to 10V p-p, Differential (optional)
DC Offset
20V max Single-Ended, Hi-Z or 15V Max @ 75Ω
Baseline Variation
Tracks sinusoidal offsets to 100% p-p signal amplitude at 0.1% bit rate
PCM Codes
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
Derandomizer
Program selectable: RNRZ 9/11/15/17/23, forward/reverse
SYNCHRONIZATION
Bit Rate Range
8bps to 40MHz, all PCM Codes
Tuning Resolution
0.1% of bit rate
Capture Range
3 times the programmed loopwidth, typical
Tracking Range
±12% typical, with programmable limiter
Loop Bandwidth
0.1% to 3.2%, program selectable in 0.1% increments
Sync Threshold
0db for NRZ-L and Biø-L codes
Sync Maintenance
(LW=0.1%) –2dB NRZ-L and Biø-L codes
Sync Acquisition
(LW=1.6%, SNR > 12dB) Typically less than 50 bit periods
Sync Retention
(LW=0.1%, SNR > 3dB) Retains sync through > 1024 consecutive dropouts
Bit Error Rate
(LW=0.1%) to within .50 dB of ideal bit error rate performance curves
DATA/CLOCK OUTPUTS, NRZ-L Per Bit Sync
NRZ-L Data
One each, NRZ-L data/clock pair, RS422/TTL (jumper selectable) – operator program output selectable to INTERNAL (direct to host decom card via internet bus) or EXTERNAL (output pair directed to card external output BNC or Triax cables)
Data Clock
0°, 90°, 180°, 270°, operator program selectable
Data Polarity
Program selectable: normal/inverted
DATA/CLOCK OUTPUTS, CODE (Dual PCM Encoders) Per Bit Sync
Data Source
Program selectable: Recovered Data (Bit Sync NRZ-L Data/Clock – DEFAULT) or External Data/Clock (PROGRAM SELECTABLE).
Outputs
Three each: One each TTL data/clock (0° & 180° selectable) Code (selectable) PCM and Clock, One each TTL data RNRZL, One each TAPE (code selectable) TTL or ±2 Volts balanced output, 50mA drive current.
Randomizer
Program selectable: RNRZ 9/11/15/17/23, forward/reverse
PCM Codes
Program selectable: NRZ-L/M/S, Biø-L//M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
EXTERNAL DATA/CLOCK PCM ENCODER INPUT Per Bit Sync
Signal Type
Jumper selectable: RS-422 or TTL
Impedence
120Ω , RS-422, 75Ω TTL
Data Code
Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ
Data Clock
Program selectable: Normal/Inverted, 1x or 2x
CONVOLUTION ENCODER/DECODER (Optional)
Viterbi Decoder
Rate 1/2, k=7: includes differential decoding, V.35 descrambling, and G2 invert (others available)
Symbol Formats
Serial, parallel, and staggered parallel (others available)
Convolution Encoder
Rate 1/2, k=7: includes differential encoder, V.35 scrambler, and G2 inverter (others available)
Symbol Formats
Serial, parallel, and staggered parallel (others available)
FORMAT GENERATORS/SYNCHRONIZER (Optional)
Format Generator
Programmable frame length, sync pattern and mask
Synchronizer Source
Recovered data, external data or test generator
Synchronizer Strategy
Pattern match in “search”, programmable error limits for “check” and “lock” states
Other Features
Bit slip enable, auto polarity enable, data source/ambiguity resolution
BIT ERROR RATE TESTER (Optional)
Transmitter Pattern
PRN sequence: PN7, PN9, PN11, PN15 (forward/reverse)
Pattern Clock Source
Program selectable: Bit Rate Clock or External Clock
Blanking
Program selectable: 64, 128, 256 bits
BER Sample Period
Program selectable: 1E3 to 1E9 bit periods, or continuous accumulate
Variable Output
50mV to 5V P-P
Other Features
Automatic pattern sychronization, forced error ON/OFF
PHYSICAL
Hosts Supported
Plugs onto Models 1611P, 1626P, 1612P, & 1622P (PCI), 1632AP (PCIe), or RS232 Standalone
Cooling Requirements
30 Linear FPM
Power Requirements
+5VDC at 1.4A and +12VDC at  0.9A
Dimensions
6.5″ (16.51cm) H x 4.0″ (310.16cm) W x .625″ (1.5875cm) D
Temperature
Operating: 0° to +40° C, Non-operating -40° to 86° C
Relative Humidity
Up to 90% non-condensing
Shock
Operating 6G, Non-operating 25G
Vibration
Operating 0.3G, 5 to 2000 Hz, Non-operating 0.8G, 5 to 500 Hz

Specifications subject to change without notice.

FILTER