Model 652 Dual Channel Data Transmission Test Set (BERT)
  • Two independent Bit Error Rate Testing (BERTs)
  • HSSI and RS-449 interfaces – up to 52Mbps operation
  • Noise, Jitter, Acquisition Time, Link Delay Measurement, and Convolutional Encoding

The GDP Model 652 Data Transmission Test Set fills the need for high performance data-link verification and qualification at an affordable price. The user is provided with two totally independent channels, and each channel provides independent transmit and receive functions. This allows for rapid fault isolation and data link characterization. Features such as an internal 6-digit frequency synthesizer and IRIG-106 Bit-Code generator and converter make the Model 652 especially suited to the test and evaluation of data link systems and components.

The Model 652 provides measurement of:
Accumulated Bit Errors, Measured Bit Error Rate, Elapsed Test Time, Accumulated Errored Seconds, Errors per Second, Accumulated Bit Count Integrity loss (Bit Slips), Measured Transmit and Receive clock rate.

Operating ease and test flexibility is the result of using microprocessor control to augment high-speed hardware functions. A high contrast vacuum fluorescent display provides setup and test result information in easy-to-use formats.

Functional Description

The unique architecture of the Model 652 provides superior flexibility. A fully programmable frequency synthesizer allows transmit clock generation from 1 bps to 52 Mbps with 6-digit resolution. A flexible interface structure, which provides IRIG-106 code converters for both input and output data, allows the Model 652 to fully support test and evaluation of telemetry processing systems.

The BER (Bit Error Rate) Module, is the major functional element in the Model 650. A microprocessor resident on the BER module controls the BERT transmit and receive circuits through user commands issued from the local front panel or remote control port. Communication between the microprocessor module and the BER module is accomplished using semaphores passed into a dual-port RAM architecture. All high-speed functions are provided by hardware

Functions such as data generation, PRN correlation, error detection and accumulation are performed by hardware. Low speed functions, such as test result accumulation and formatting for the front panel and remote monitoring ports, are provided by the embedded microprocessors.

Expansion slots are provided for addition of options.

Model 652 Dual Channel Data Transmission Test Set (BERT)
  • Two independent Bit Error Rate Testing (BERTs)
  • HSSI and RS-449 interfaces – up to 52Mbps operation
  • Noise, Jitter, Acquisition Time, Link Delay Measurement, and Convolutional Encoding

The GDP Model 652 Data Transmission Test Set fills the need for high performance data-link verification and qualification at an affordable price. The user is provided with two totally independent channels, and each channel provides independent transmit and receive functions. This allows for rapid fault isolation and data link characterization. Features such as an internal 6-digit frequency synthesizer and IRIG-106 Bit-Code generator and converter make the Model 652 especially suited to the test and evaluation of data link systems and components.

The Model 652 provides measurement of:
Accumulated Bit Errors, Measured Bit Error Rate, Elapsed Test Time, Accumulated Errored Seconds, Errors per Second, Accumulated Bit Count Integrity loss (Bit Slips), Measured Transmit and Receive clock rate.

Operating ease and test flexibility is the result of using microprocessor control to augment high-speed hardware functions. A high contrast vacuum fluorescent display provides setup and test result information in easy-to-use formats.

Functional Description

The unique architecture of the Model 652 provides superior flexibility. A fully programmable frequency synthesizer allows transmit clock generation from 1 bps to 52 Mbps with 6-digit resolution. A flexible interface structure, which provides IRIG-106 code converters for both input and output data, allows the Model 652 to fully support test and evaluation of telemetry processing systems.

The BER (Bit Error Rate) Module, is the major functional element in the Model 650. A microprocessor resident on the BER module controls the BERT transmit and receive circuits through user commands issued from the local front panel or remote control port. Communication between the microprocessor module and the BER module is accomplished using semaphores passed into a dual-port RAM architecture. All high-speed functions are provided by hardware

Functions such as data generation, PRN correlation, error detection and accumulation are performed by hardware. Low speed functions, such as test result accumulation and formatting for the front panel and remote monitoring ports, are provided by the embedded microprocessors.

Expansion slots are provided for addition of options.

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