Bit Synchronizers

Model 2265 Single/Dual/Quad Bit Synchronizer

The GDP Model 2265 Multi-Channel PCM Bit Synchronizer houses up to 4 high-performance bit synchronizer channels in a 2U chassis. The optimized digital design of this unit affords the highest performance characteristics currently available.

The Model 2265 is capable of maintaining synchronization with the signal of interest down to –3 dB Eb/No at signal levels down to 100mVpp. When searching for the signal, acquisition is attainable in less than 50 bits. The unit is very robust and can maintain synchronization for a period of at least 256 bit periods without a transition.

The standard IRIG randomizer/derandomizer for both forward and reverse sequences is provided. CCITT V.35 and V.36 scrambling/descrambling is also provided. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7 and R1/3 k7 (please inquire for other FEC options).

To assure synchronization to the intended data stream, the Frame Pattern Detector may be invoked. Up to a 64-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. An Automatic Polarity Correction (APC) mode is also provided for inverted data.

Each of the channels include four Analog inputs. Additional inputs are optionally available for RS-422 and TTL levels. Each channel also has a variety of outputs that include; three independent programmable TTL Coded PCM outputs and one TTL Auxiliary Coded output (4 total), two independently programmable (0, 90, 180 and 270 degree) TTL Clock outputs and one TTL Auxiliary Clock output (3 total), two RS-422 Coded PCM and two RS-422 Clock outputs. Front Panel Monitor BNCs are provided for each channel that include one Selected Input Monitor, one PCM Data Out and one Clock Out.

The MD2265 includes several unique features to determine the quality of the data. The first is an Eb/No (Signal Quality) measurement. From this measurement, the error rate of the data can be determined. The MD2265 also measured errors in the frame synchronizer pattern as well as errors in the Viterbi stream when these modes are enabled. A bit-error-rate (BERT) function is also provided. This allows link test in a short loop back to verify proper operation of the module, or long loop-back to measure performance of the link. An advanced lock detector ensures a solid lock indication for the module.

The Auto Scan feature is available to scan the input for up to 8 combinations of bit rates, input codes and frame patterns (per Bit Sync). When one of the signals is present, the Bit Sync automatically locks onto it and recovers the data and clock.

  1. Up to 4 Channels per 2U Box
  2. Bit Rates
  3.      • 5 bps to 20 Mbps
         • 5 bps to 40 Mbps (Opt)
  4. Performance within 1 dB of theory
  5. Advanced Lock Detention
  6. Loop Bandwidth Settings from 0.01% to 1.6%
  7.      • Extended LBW Range (Opt)
  8. Accepts NRZ-L/M/S, BiØ-L/M/S, DM-M/S; MDM-M/S
  9. Bit Rate Deviation Indication
  10. Randomizer/Derandomizer
  11. Scrambler/Descrambler
  12.      • CCITT V.35/36
  13. Convolution Encoder
  14. Viterbi Decoder
  15. Frame Pattern Detector
  16. Input Signal Status
  17.      • Sync and Loss
         • Measured Input Bit Rate
         • Measured Signal Level
         • Input Data Polarity
  18. Signal/Data Quality Status
  19.      • Eb/No Measurement
         • BER/CER Measurement BERT PRN
         • Signal Level Measurement
  20. Date Generator/Simulator
  21.      • Serial and QPSK(Opt)
  22. Auto Bit-Rate Scan (Opt)
  23. OPSK/OQPSK/SOQPSK Resequencer (opt)
  24. Remote Control via.
  25.      • RS-232 (Std)
         • Ethernet (Opt)
         • IEEE-488 (Opt)
Inputs, each Bit Sync
Analog Inputs
Up to 4 Inputs per Bit Sync- 50 ohms (optional 75) or High Z (Transition Module Dependent)
Digital Inputs
Differential RS-422 and TTL (Optional)

Bit Rate Range
5bps to 20 Mbps (40 Mbps Optional)
Tuning Resolution
X.XXXEN (1≤N≤7)
Input Levels
0.1 Vpp Min., ± 12 V Max.. (others available)
DC Offsets
DC Offset + peak input signal without exceeding Level limits.
AC Offset
No degradation up to 100% of input signal amplitude at 0.1% of the bit rate.
Loop Bandwidths
0.01% to 1.6% (Extended LBW Range Optional)
Acquisition Range
2x LBW
Sync Acquisition Threshold
SNR 0 dB
Sync Maintenance
SNR –3dB
Sync Acquisition
< 50 bits
Sync Retention
256 bits without transitions
Bit Error Rate
1 dB to 40 Mbps

Input/Output PCM Codes
IRIG 106 forward and reverse
CCITT V.35/V.36
Viterbi Decoder
R 1/2, K 7 with G1/G2 Swap and G2 Invert, (others available)
Frame Pattern Detector
Up to 64 bits with programmable strategy and APC
Auto Scan (Optional)
Searches up to 8 Bit Rate, Code, Frame pattern combos per Bit Sync
Output Data Polarity
Input polarity normal / inverted.
Output Clock Phase
0, 90, 180 & 270 degrees to 20 Mbps; 0 & 180 degrees, 20Mbps to 40Mbps
BERT Function
Bit-Error-Rate PRN Generator/Error Detector (opt)

Outputs, each Bit Sync Channel
TTL (Each Channel)
Coded PCM and Clocks (Programmable 0, 90, 180, 270 degrees)
RS422 (Each Channel)
Coded PCM and Clock (Programmable 0, 90, 180, 270 degrees)
Bipolar Tape Output (Each Channel)

± 1V - Coded PCM
Front Panel Monitor (Each Channel)

Selected Input Monitor, PCM Data Out, Clock Out
Composite Lock Status
Bit Synchronization, Frame Pattern and Viterbi
Signal Quality Status:
Presented on Front Panel and Remote Port:
Bit Sync Lock, Eb/No, Bit Rate Deviation, Signal Presence, Signal Level, Bit Sync Lock-Loss-Count, and PRN BER/CER